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dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorFan, Chia-Chien_US
dc.contributor.authorLiu, Chienen_US
dc.contributor.authorChiu, Yu-Chienen_US
dc.contributor.authorCheng, Chun-Huen_US
dc.date.accessioned2018-08-21T05:57:08Z-
dc.date.available2018-08-21T05:57:08Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn2162-7541en_US
dc.identifier.urihttp://hdl.handle.net/11536/147095-
dc.description.abstractThis work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.en_US
dc.language.isoen_USen_US
dc.titleHigh Speed Negative Capacitance Ferroelectric Memoryen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)en_US
dc.citation.spage1en_US
dc.citation.epage5en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000426983400001en_US
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