標題: New Digit-Serial Three-Operand Multiplier over Binary Extension Fields for High-Performance Applications
作者: Lee, Chiou-Yng
Fan, Chia-Chen
Yuan, Shyan-Ming
交大名義發表
National Chiao Tung University
關鍵字: three-operand multiplication;digit-serial multiplier;binary extension fields
公開日期: 1-Jan-2017
摘要: Digit-serial polynomial basis multipliers over GF(2(m)) are broadly applied in elliptic curve cryptography, because squaring and polynomial reduction in GF(2(m)) are simple operations. In this paper, we define a partial product formula to derive a new digit-serial three-operand multiplication algorithm. On the basis of the proposed algorithm, we have derived a new digit-serial structures for computing three-operand multiplication. Our proposed structures can reduce latency (clock cycles) by approximately 50% compared to the existing digit-serial two-operand multipliers used to perform three-operand multiplication. Therefore, the proposed structure can achieve high-throughput designs. According to the analysis reports, the advantages of the proposed designs are a short critical path, a low area-delay product, and a high throughput.
URI: http://dx.doi.org/10.1109/CIAPP.2017.8167267
http://hdl.handle.net/11536/146960
DOI: 10.1109/CIAPP.2017.8167267
期刊: 2017 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND APPLICATIONS (ICCIA)
起始頁: 498
結束頁: 502
Appears in Collections:Conferences Paper