完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, Yen-Tingen_US
dc.contributor.authorYang, Wen-Hauen_US
dc.contributor.authorMa, Yu-Shengen_US
dc.contributor.authorLai, Yan-Jiunen_US
dc.contributor.authorChen, Hung-Weien_US
dc.contributor.authorChen, Ke-Horngen_US
dc.contributor.authorWey, Chin-Longen_US
dc.contributor.authorLin, Ying-Hsien_US
dc.contributor.authorLin, Jian-Ruen_US
dc.contributor.authorTsai, Tsung-Yenen_US
dc.date.accessioned2018-08-21T05:57:05Z-
dc.date.available2018-08-21T05:57:05Z-
dc.date.issued2017-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/147026-
dc.description.abstractDifferent from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the destined ratio rapidly and to reduce the transient recovery time. Experimental results show the test chip fabricated in 0.25 mu m CMOS process increases the ratio number to 187 and 2389 in 3-stage and 4-stage SC regulators, respectively. Transient recovery time reduces from 26 mu s to 1.5 mu s in case of 7mA load current step.en_US
dc.language.isoen_USen_US
dc.subjectUnsymmetrical parallel switched-capacitor (UP-SC)en_US
dc.subjectfast searching optimum ratio (FSOR) techniqueen_US
dc.subjectwide voltage conversion ratioen_US
dc.titleUnsymmetrical Parallel Switched-Capacitor (UP-SC) Regulator with Fast Searching Optimum Ratio Techniqueen_US
dc.typeProceedings Paperen_US
dc.identifier.journalESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCEen_US
dc.citation.spage287en_US
dc.citation.epage290en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000426841900072en_US
顯示於類別:會議論文