標題: | A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering |
作者: | Tseng, Yu-Cheng Hsu, Po-Hsiung Chang, Tian-Sheuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Bilateral filtering (BF);integral histogram (IH);very-large-scale-integration (VLSI) design |
公開日期: | 1-十一月-2011 |
摘要: | This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory. |
URI: | http://dx.doi.org/10.1109/TIP.2011.2159226 http://hdl.handle.net/11536/14707 |
ISSN: | 1057-7149 |
DOI: | 10.1109/TIP.2011.2159226 |
期刊: | IEEE TRANSACTIONS ON IMAGE PROCESSING |
Volume: | 20 |
Issue: | 11 |
起始頁: | 3231 |
結束頁: | 3241 |
顯示於類別: | 期刊論文 |