The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines

Abstract

A theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and I-g current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large I-on current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide- thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.