完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, D. -C. | en_US |
dc.contributor.author | Hsieh, E. Ray | en_US |
dc.contributor.author | Gong, J. | en_US |
dc.contributor.author | Huang, C. -F. | en_US |
dc.contributor.author | Chung, Steve S. | en_US |
dc.date.accessioned | 2018-08-21T05:57:09Z | - |
dc.date.available | 2018-08-21T05:57:09Z | - |
dc.date.issued | 2017-01-01 | en_US |
dc.identifier.issn | 1946-1550 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/147119 | - |
dc.description.abstract | This study investigates the bias temperature instability in high-k/metal-gate pMOSFETs with a TiN barrier layer sandwiched between the metal gate electrode and HfO2 dielectric and for reliability improvement of such devices. The experimental results clearly demonstrated that the diffusion mechanism of oxygen and nitrogen resulting from the post metallization treatment was the root cause of bias temperature instabilities in the p-channel MOSFETs. However, the device NBTI reliability is dependent on the nitrogen diffusion from the TiN layer, which degrades the SiO2/Si interfacial layer quality. Results show that by increasing the thickness of TiN barrier layer, the driving current will make worse the NBTI in p-MOSFET. Therefore, optimization needs to be considered for TiN as a barrier to improve the device reliabilities. | en_US |
dc.language.iso | en_US | en_US |
dc.title | The Impact of TiN Barrier on the NBTI in an Advanced High-k Metal-gate p-channel MOSFET | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000426989100159 | en_US |
顯示於類別: | 會議論文 |