標題: | Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices |
作者: | Yang, Hao-I Hwang, Wei Chuang, Ching-Te 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Contact resistance;negative bias temperature instability (NBTI);positive bias temperature instability (PBTI);power-gated SRAM;reliability |
公開日期: | 1-七月-2011 |
摘要: | The threshold voltage (V(TH)) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term V(TH) drifts degrade SRAM cell stability, margin, and performance, and may lead to functional failure over the life of usage. Meanwhile, the contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-ground rule devices. The contact resistance, together with NBTI/PBTI, cumulatively worsens the SRAM stability, and leads to severe SRAM performance degradation. Furthermore, most state-of-the-art SRAMs are designed with power-gating structures to reduce leakage currents in Standby or Sleep mode. The power switches could suffer NBTI or PBTI degradation and have large contact resistances. This paper presents a comprehensive analysis on the impacts of NBTI and PBTI on power-gated SRAM arrays with high-k metal-gate devices and the combined effects with the contact resistance on SRAM cell stability, margin, and performance. NBTI/PBTI tolerant sense amplifier structures are also discussed. |
URI: | http://dx.doi.org/10.1109/TVLSI.2010.2049038 http://hdl.handle.net/11536/22187 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2010.2049038 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 19 |
Issue: | 7 |
起始頁: | 1192 |
結束頁: | 1204 |
顯示於類別: | 期刊論文 |