Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices

Abstract

The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, V(T). drifts Caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of natroscale SPAM with high-kappa, metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.