標題: | Effect of graded-temperature arsenic prelayer on quality of GaAs on Ge/Si substrates by metalorganic vapor phase epitaxy |
作者: | Yu, H. W. Chang, E. Y. Yamamoto, Y. Tillack, B. Wang, W. C. Kuo, C. I. Wong, Y. Y. Nguyen, H. Q. 材料科學與工程學系 電子工程學系及電子研究所 Department of Materials Science and Engineering Department of Electronics Engineering and Institute of Electronics |
公開日期: | 24-Oct-2011 |
摘要: | The growth of GaAs epitaxy on Ge/Si substrates with an arsenic prelayer grown with graded temperature ramped from 300 to 420 degrees C is investigated. It is demonstrated that the graded-temperature arsenic prelayer grown on a Ge/Si substrate annealed at 650 degrees C not only improves the surface morphology (roughness: 1.1 nm) but also reduces the anti-phase domains' (APDs) density in GaAs epitaxy (dislocation density: similar to 2 x 10(7) cm(-2)). Moreover, the unwanted interdiffusion between Ge and GaAs epitaxy is suppressed by using the graded-temperature arsenic prelayer due to the low energy of the Ge-As bond and the use of a low V/III ratio of 20. (C) 2011 American Institute of Physics. [doi:10.1063/1.3656737] |
URI: | http://dx.doi.org/10.1063/1.3656737 http://hdl.handle.net/11536/14724 |
ISSN: | 0003-6951 |
DOI: | 10.1063/1.3656737 |
期刊: | APPLIED PHYSICS LETTERS |
Volume: | 99 |
Issue: | 17 |
結束頁: | |
Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.