標題: Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
作者: Luo, Tseng-Chin
Chao, Mango C. -T.
Tseng, Huan-Chi
Goto, Masaharu
Fisher, Philip A.
Chang, Yuan-Yao
Chang, Chi-Min
Takao, Takayuki
Iwasaki, Katsuhito
Lee, Cheng Mao
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Design for manufacturing (DFM);Threshold voltage;Variation
公開日期: 1-五月-2014
摘要: As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
URI: http://dx.doi.org/10.1109/TVLSI.2013.2265299
http://hdl.handle.net/11536/147697
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2013.2265299
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 22
起始頁: 1138
結束頁: 1149
顯示於類別:期刊論文