Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chiang, Che-Yang | en_US |
dc.contributor.author | Hsu, Heng-Tung | en_US |
dc.contributor.author | Wang, Chin-Te | en_US |
dc.contributor.author | Kuo, Chien-I | en_US |
dc.contributor.author | Hsu, Heng-Shou | en_US |
dc.contributor.author | Chang, Edward Yi | en_US |
dc.date.accessioned | 2014-12-08T15:20:45Z | - |
dc.date.available | 2014-12-08T15:20:45Z | - |
dc.date.issued | 2011-10-01 | en_US |
dc.identifier.issn | 1882-0778 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/APEX.4.104105 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/14769 | - |
dc.description.abstract | This study fabricated a 150 nm In(0.6)Ga(0.4)As metamorphic high-electron-mobility transistor (mHEMT) device with flip-chip packaging. The packaged device exhibited favorable DC characteristics with I(DS) = 350 mA/mm and a transconductance of 600 mS/mm at V(DS) = 0.5V. A maximum available gain (MAG) of 6.5 dB at 60 GHz was achieved with 10 mW DC power consumption. A two-stage gain block was designed and fabricated. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20 mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal-oxide-semiconductor (CMOS) technology with lower power consumption. (C) 2011 The Japan Society of Applied Physics | en_US |
dc.language.iso | en_US | en_US |
dc.title | V-Band Flip-Chip Assembled Gain Block Using In(0.6)Ga(0.4)As Metamorphic High-Electron-Mobility Transistor Technology | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/APEX.4.104105 | en_US |
dc.identifier.journal | APPLIED PHYSICS EXPRESS | en_US |
dc.citation.volume | 4 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | en_US | |
dc.citation.epage | en_US | |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
Appears in Collections: | Articles |