Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

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DC 欄位	值	語言
dc.contributor.author	Liu, Yu-Sian	en_US
dc.contributor.author	Wen, Kuei-Ann	en_US
dc.date.accessioned	2019-04-02T06:01:00Z	-
dc.date.available	2019-04-02T06:01:00Z	-
dc.date.issued	2018-12-01	en_US
dc.identifier.issn	2072-666X	en_US
dc.identifier.uri	http://dx.doi.org/10.3390/mi9120637	en_US
dc.identifier.uri	http://hdl.handle.net/11536/148681	-
dc.description.abstract	A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 m CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 g/Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.	en_US
dc.language.iso	en_US	en_US
dc.subject	Accelerometer readout	en_US
dc.subject	low noise	en_US
dc.subject	low zero-g offset	en_US
dc.title	Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme	en_US
dc.type	Article	en_US
dc.identifier.doi	10.3390/mi9120637	en_US
dc.identifier.journal	MICROMACHINES	en_US
dc.citation.volume	9	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000455072800028	en_US
dc.citation.woscount	1	en_US
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