加速度計設計與低功率電容轉頻率讀出電路

Abstract

本論文提出一建立在混合信號微機電製程下具電容轉頻率讀出電路之單晶加速度計設計。利用積分器與比較器跟數位電路將感測訊號轉換成頻率相關訊號。與其它電容轉電壓讀出電路加類比轉數位轉換器比較下，電容轉頻率轉換器能減少硬體成本。在不包含加速度計的情況下,總面積為0.356mm*0.609mm。 讀出電路使用積分器配合截波穩定技術來消除閃爍雜訊與電壓偏移.電路上使用UMC 0.18um製程。根據Spectre RF模擬結果,積分器的均方根雜訊為636.6uV。雜訊的積分範圍在0~500 kHz。在使用改進的電容轉頻率讀出電路架構下，達到低功率及高解析度的目的。 根據實驗與量測結果顯示在1.8V電源供應下，功率與電路敏感度分別為225.77uW跟731.26 Hz/fF。

A monolithic accelerometer with integrated capacitance to frequency readout in mixed signal MEMS process is proposed. It directly converts to the frequency dependent signal by the integrator, the comparator and the digital logic circuit. Compared with capacitance to voltage readout circuit and analog to digital converter, the C to F converter can reduce the amount of hardware. The total area is 0.356mm*0.609mm without accelerometer. The readout circuit employs the switch capacitance charge integrator with chopper stabilization to suppress the flicker noise and offset. The integrator output rms noise is 636.6uV (integrating from 0 Hz~500 kHz) by Spectre RF simulation in UMC 0.18um technology. Due to the modified capacitance to frequency readout circuit structure, it can achieve the goal of low power and high resolution. The total power consumption and the circuit sensitivity are 225.77uW and 731.26 Hz/fF at 1.8V power supply by measurement result.