標題: 具偏移補償讀出電路之單晶CMOS MEMS加速度計
Monolithic Accelerometer and Readout Circuit with Offset Cancellation Design
作者: 林建原
Lin, Chien-Yuan
溫瓌岸
Wen, Kuei-Ann
電子研究所
關鍵字: 微機電;單晶;加速度計;截波穩定;運算放大器;數位類比轉換器;MEMS;Monolithic;Accelerometer;Chopper stabilization;Operational amplifier;DAC
公開日期: 2010
摘要: 本論文提出一建立在混合信號微機電製程下具偏移補償讀出電路之單晶加速度計設計。讀出電路採用連續時間感測與截波穩定以減輕噪聲問題。為讀取加速度信號和大幅度抵銷加速度計因位置誤差而產生之直流偏移,此電路利用運算放大器的電容性回授網絡產生精確增益和偏移補償。少位元數位類比轉換器被利用在兩階段式的偏移補償。根據模擬結果,20%加速度計位移偏移可以被補正且帶有可忽略的性能偏移。實驗與量測結果顯示設計的加速度計直流輸出電壓偏移可大部分被矯正回來並具有70 mV/G加速度訊號增益在 ±2G的輸入範圍內。解析度為400μG/√Hz。
A monolithic accelerometer with integrated readout and sensor offset compensation circuit in mixed-signal MEMS process is proposed to extract the sensor signal and highly reject its offset. The readout circuit employs continuous time voltage sensing with chopper stabilization to alleviate 1/f noise issue. The circuit gain and sensor offset compensation are controlled accurately by the capacitor values in the op amps capacitive feedback networks. Utilizing two-stage offset cancellation, position offset in the sensor is highly compensated by digital input of coarse DAC. Supported by the simulation, 20% sensor mismatch condition is mostly corrected by the digitalized compensation circuitry with negligible performance variation compared from the condition without sensor offset. By experimental result, output offset voltage of the accelerometer is mostly cancelled by digital input to compensation circuit. With 400μG/√Hz noise floor, the accelerometer archives 70 mV/G overall sensitivity in ±2G input range.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811648
http://hdl.handle.net/11536/46815
顯示於類別:畢業論文