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dc.contributor.authorHu, Si-Yuen_US
dc.contributor.authorLi, Yien_US
dc.contributor.authorCheng, Longen_US
dc.contributor.authorWang, Zhuo-Ruien_US
dc.contributor.authorChang, Ting-Changen_US
dc.contributor.authorSze, Simon M.en_US
dc.contributor.authorMiao, Xiang-Shuien_US
dc.date.accessioned2019-04-02T06:00:28Z-
dc.date.available2019-04-02T06:00:28Z-
dc.date.issued2019-02-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2018.2886364en_US
dc.identifier.urihttp://hdl.handle.net/11536/148816-
dc.description.abstractIn-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a 4 x 3 array has been designed and verified in simulation.en_US
dc.language.isoen_USen_US
dc.subjectMemristoren_US
dc.subjectcrossbar arrayen_US
dc.subjectBoolean logicen_US
dc.subjectreconfigurableen_US
dc.subjectin-memory computingen_US
dc.titleReconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2018.2886364en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume40en_US
dc.citation.spage200en_US
dc.citation.epage203en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000457606300011en_US
dc.citation.woscount0en_US
Appears in Collections:Articles