Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | CHENG, JY | en_US |
dc.contributor.author | LEI, TF | en_US |
dc.contributor.author | CHAO, TS | en_US |
dc.date.accessioned | 2019-04-02T05:59:28Z | - |
dc.date.available | 2019-04-02T05:59:28Z | - |
dc.date.issued | 1995-10-01 | en_US |
dc.identifier.issn | 0013-4651 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1149/1.2050039 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/149144 | - |
dc.description.abstract | The planarization of trench isolation refilled by deposition oi polysilicon was investigated. Results show that the planarization by RIE etching has poor surface planarity. On the other hand, an excellent surface planarity can be achieved by the CMP process resulting from the high etching selectivity of polysilicon to nitride. This simple process provides a very promising candidate for trench isolation. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A NOVEL PLANARIZATION OF TRENCH ISOLATION USING POLYSILICON REFILL AND ETCHBACK OF CHEMICAL-MECHANICAL POLISH | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.2050039 | en_US |
dc.identifier.journal | JOURNAL OF THE ELECTROCHEMICAL SOCIETY | en_US |
dc.citation.volume | 142 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1995RZ32800008 | en_US |
dc.citation.woscount | 2 | en_US |
Appears in Collections: | Articles |