完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Chia-Wen | en_US |
dc.date.accessioned | 2019-04-02T06:01:01Z | - |
dc.date.available | 2019-04-02T06:01:01Z | - |
dc.date.issued | 2007-01-01 | en_US |
dc.identifier.issn | 0013-4651 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1149/1.2778858 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/149246 | - |
dc.description.abstract | High-performance solid-phase crystallized (SPC) polycrystalline silicon thin-film transistors (TFTs) with argon ion implantation (argon-implanted poly-Si TFTs) are proposed in this study. Compared to the control poly-Si TFT, the argon-implanted poly-Si TFT has superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, steeper subthreshold swing, lower trap state density, etc. These electrical performance improvements could be attributed to the fine microstructure of the SPC poly-Si film improved by deep argon ion implantation beyond the interface of amorphous Si and underlying oxide. Therefore, a high-quality poly-Si channel accompanied with larger grain size and lower grain boundary trap states could be obtained. Moreover, the argon-implanted poly-Si TFT also exhibits an improved hot-carrier stress immunity owing to reduced weak Si-Si or Si-H bonds from fewer grain boundaries in the poly-Si channel. (c) 2007 The Electrochemical Society. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Enhanced performance and reliability for solid-phase crystallized poly-Si TFTs with argon ion implantation | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.2778858 | en_US |
dc.identifier.journal | JOURNAL OF THE ELECTROCHEMICAL SOCIETY | en_US |
dc.citation.volume | 154 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000249787900086 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 期刊論文 |