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dc.contributor.authorLin, Chia-Yien_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2014-12-08T15:21:02Z-
dc.date.available2014-12-08T15:21:02Z-
dc.date.issued2011-11-01en_US
dc.identifier.issn1016-2364en_US
dc.identifier.urihttp://hdl.handle.net/11536/14943-
dc.description.abstractThis paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the scheme to a generic N dimension test scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed 2-D scheme achieve significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead, around 1% routing overhead, and the power reduction is over 97%.en_US
dc.language.isoen_USen_US
dc.subjectDFTen_US
dc.subjectlow poweren_US
dc.subjectscan chainen_US
dc.subjectcompressionen_US
dc.subjecttest data volumeen_US
dc.titleA Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reductionen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF INFORMATION SCIENCE AND ENGINEERINGen_US
dc.citation.volume27en_US
dc.citation.issue6en_US
dc.citation.spage1943en_US
dc.citation.epage1957en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000297605900010-
dc.citation.woscount0-
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