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dc.contributor.authorLin, Chin-Tengen_US
dc.contributor.authorYu, Yuan-Chuen_US
dc.contributor.authorVan, Lan-Daen_US
dc.date.accessioned2019-04-02T06:01:07Z-
dc.date.available2019-04-02T06:01:07Z-
dc.date.issued2008-08-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2008.2000676en_US
dc.identifier.urihttp://hdl.handle.net/11536/149490-
dc.description.abstractThis investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.en_US
dc.language.isoen_USen_US
dc.subjectcomputation complexityen_US
dc.subjectcost effectiveen_US
dc.subjecthardware utilizationen_US
dc.subjectnext-generation wireless communicationsen_US
dc.subjectpipeline architectureen_US
dc.subjectR4(2)SDFen_US
dc.subjecttriple modesen_US
dc.titleCost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processoren_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2008.2000676en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume16en_US
dc.citation.spage1058en_US
dc.citation.epage1071en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電機學院zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000257987400011en_US
dc.citation.woscount18en_US
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