An 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiver

doi:10.1109/ASSCC.2009.5357153

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DC 欄位	值	語言
dc.contributor.author	Wu, Guo-Wei	en_US
dc.contributor.author	Chen, Wei-Zen	en_US
dc.contributor.author	Huang, Shih-Hao	en_US
dc.date.accessioned	2014-12-08T15:21:05Z	-
dc.date.available	2014-12-08T15:21:05Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-4434-2	en_US
dc.identifier.uri	http://hdl.handle.net/11536/14997	-
dc.identifier.uri	http://dx.doi.org/10.1109/ASSCC.2009.5357153	en_US
dc.description.abstract	An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 mu m CMOS technology, the chip size is 0.62 mm x 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.	en_US
dc.language.iso	en_US	en_US
dc.subject	automatic gain control (AGC)	en_US
dc.subject	variable gain amplifier	en_US
dc.subject	PAM receiver	en_US
dc.title	An 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiver	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/ASSCC.2009.5357153	en_US
dc.identifier.journal	2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)	en_US
dc.citation.spage	173	en_US
dc.citation.epage	176	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000298194200044	-
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