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dc.contributor.authorWu, Guo-Weien_US
dc.contributor.authorChen, Wei-Zenen_US
dc.contributor.authorHuang, Shih-Haoen_US
dc.date.accessioned2014-12-08T15:21:05Z-
dc.date.available2014-12-08T15:21:05Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4434-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/14997-
dc.identifier.urihttp://dx.doi.org/10.1109/ASSCC.2009.5357153en_US
dc.description.abstractAn 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 mu m CMOS technology, the chip size is 0.62 mm x 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.en_US
dc.language.isoen_USen_US
dc.subjectautomatic gain control (AGC)en_US
dc.subjectvariable gain amplifieren_US
dc.subjectPAM receiveren_US
dc.titleAn 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiveren_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ASSCC.2009.5357153en_US
dc.identifier.journal2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage173en_US
dc.citation.epage176en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000298194200044-
Appears in Collections:Conferences Paper


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