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dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorLin, Chih-Hsienen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorLu, Hung-Wenen_US
dc.contributor.authorSu, Chau-Chinen_US
dc.contributor.authorHong, Kai-Weien_US
dc.contributor.authorCheng, Kuo-Hsingen_US
dc.contributor.authorYang, Shyue-Wenen_US
dc.contributor.authorSheu, Ming-Hwaen_US
dc.date.accessioned2014-12-08T15:21:06Z-
dc.date.available2014-12-08T15:21:06Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4434-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/14999-
dc.identifier.urihttp://dx.doi.org/10.1109/ASSCC.2009.5357256en_US
dc.description.abstractIn this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 mu m CMOS technology. The core area of this chip is 990 mu m*1600 mu m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.en_US
dc.language.isoen_USen_US
dc.titleA Micro-Network on Chip with 10-Gb/s Transmission Linken_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ASSCC.2009.5357256en_US
dc.identifier.journal2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage277en_US
dc.citation.epage280en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000298194200070-
Appears in Collections:Conferences Paper


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