A Micro-Network on Chip with 10-Gb/s Transmission Link

doi:10.1109/ASSCC.2009.5357256

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liu, Wei-Chang	en_US
dc.contributor.author	Lin, Chih-Hsien	en_US
dc.contributor.author	Jou, Shyh-Jye	en_US
dc.contributor.author	Lu, Hung-Wen	en_US
dc.contributor.author	Su, Chau-Chin	en_US
dc.contributor.author	Hong, Kai-Wei	en_US
dc.contributor.author	Cheng, Kuo-Hsing	en_US
dc.contributor.author	Yang, Shyue-Wen	en_US
dc.contributor.author	Sheu, Ming-Hwa	en_US
dc.date.accessioned	2014-12-08T15:21:06Z	-
dc.date.available	2014-12-08T15:21:06Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-4434-2	en_US
dc.identifier.uri	http://hdl.handle.net/11536/14999	-
dc.identifier.uri	http://dx.doi.org/10.1109/ASSCC.2009.5357256	en_US
dc.description.abstract	In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 mu m CMOS technology. The core area of this chip is 990 mu m*1600 mu m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.	en_US
dc.language.iso	en_US	en_US
dc.title	A Micro-Network on Chip with 10-Gb/s Transmission Link	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/ASSCC.2009.5357256	en_US
dc.identifier.journal	2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)	en_US
dc.citation.spage	277	en_US
dc.citation.epage	280	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000298194200070	-
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