標題: | A Sub-100 mu W Area-Efficient Digitally-Controlled Oscillator Based on Hysteresis Delay Cell Topologies |
作者: | Chen, Man-Chia Yu, Jui-Yuan Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2009 |
摘要: | This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous one in a descending order, resulting in low power and low cost features. A self-calibration method is accompanied to maintain the monotonicity of the P2DCO under PVT variations. The P2DCO is verified in a 90nm CMOS technology. The LSB control word provides a 2.04ps delay resolution. The post-layout simulations show that the dynamic power is 75.9 mu W and 5.2 mu W in the 239.2MHz and 3.89MHz, respectively. The area of the P2DCO is 60*2 mu m(2). |
URI: | http://hdl.handle.net/11536/15004 http://dx.doi.org/10.1109/ASSCC.2009.5357186 |
ISBN: | 978-1-4244-4434-2 |
DOI: | 10.1109/ASSCC.2009.5357186 |
期刊: | 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) |
起始頁: | 89 |
結束頁: | 92 |
顯示於類別: | 會議論文 |