完整後設資料紀錄
DC 欄位語言
dc.contributor.authorYeh, Chih-Tingen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2019-04-02T06:00:28Z-
dc.date.available2019-04-02T06:00:28Z-
dc.date.issued2010-11-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2010.2075370en_US
dc.identifier.urihttp://hdl.handle.net/11536/150107-
dc.description.abstractThe RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.en_US
dc.language.isoen_USen_US
dc.subjectBig field-effect transistor (BigFET)en_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectholding voltageen_US
dc.subjectpower-rail ESD clamp circuiten_US
dc.titleCapacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protectionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2010.2075370en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume45en_US
dc.citation.spage2476en_US
dc.citation.epage2486en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000283442500026en_US
dc.citation.woscount22en_US
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