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dc.contributor.authorTseng, Yu-Chengen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2019-04-02T06:00:22Z-
dc.date.available2019-04-02T06:00:22Z-
dc.date.issued2010-11-01en_US
dc.identifier.issn1051-8215en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSVT.2010.2087434en_US
dc.identifier.urihttp://hdl.handle.net/11536/150139-
dc.description.abstractBelief propagation based algorithms perform best in disparity estimation but suffer from high computational complexity and storage, especially in message passing. This paper proposes an efficient architecture design with three techniques to solve the problems. For the memory storage, we propose the spinning-message and the sliding-bipartite node plane that can reduce memory cost to 1.2% for image-scale algorithms and 23.4% for block-scale algorithms, when compared to the traditional approach. For the logic complexity, we propose a buffer-free processing element architecture that has 3.6 times hardware efficiency of the previous work. The three proposed techniques could be applied to various belief propagation based algorithms to save significant hardware cost as well as approach real-time speed.en_US
dc.language.isoen_USen_US
dc.subjectBelief propagationen_US
dc.subjectdisparity estimationen_US
dc.titleArchitecture Design of Belief Propagation for Real-Time Disparity Estimationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSVT.2010.2087434en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGYen_US
dc.citation.volume20en_US
dc.citation.spage1555en_US
dc.citation.epage1564en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000283952100015en_US
dc.citation.woscount1en_US
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