1920x1080@90fps 之深度運算設計與實作

Abstract

隨著立體電視的問世，人們可以藉由立體視訊獲得新的視覺經驗。立體視訊可以立體攝影機擷取，並經由影像處理技術運算後，可支援多視角與自由視點之立體電視應用。在立體視訊的處理中，視差估測為最重要的技術之一。視差估測可產生拍攝場景之視差圖，可用於虛擬視角視訊的合成。動態影像壓縮標準組織的立體視訊編碼團隊已提出目前最先進視差估測演算法。其演算法可針對立體電視的應用產生高品質的視差圖，但因採用圖形切割演算法導致高運算複雜度與低平行運算的問題。特別對於高畫質視訊，其問題更為嚴重。 為解決以上問題，本論文提改良過的雙向動態規劃演算法，利用參考邊界資訊的遮蔽處理、方向性投票機制、以及利用邊界資訊處理不同時間嚇得像素穩定性，以達到高品質書度運算輸出之需求。另外本文亦提出深度傳輸之演算法，可以有效降低運算時間至50%以上。另一方面，針對超大型積體電路設計，本文提出之硬體架構可以合成出以下數據之電路：1920x1080@90fps，另外電路的閘數量為2,325K ，使用UMC 90nm CMOS製成合成。

Disparity estimation is one of the most interesting and important research topics in the field of stereo TV application. Accurate estimation of disparity can significantly improve the visual experience on the stereo image but at the expense of noticeable computational complexity consumptions. In this thesis, several techniques are proposed to improve the accuracy of estimated disparity results at a low memory cost. The edge detection algorithm is first adopted in the proposed algorithm to derive the important image content features and edge information for making the upcoming disparity estimation process gets more precise results. Afterwards, the proposed disparity propagation will take the edge information both from vertical and horizontal direction into account for deciding whether the disparity should be propagated from the edge area to the texture-less area. After the disparity propagation phase, the un-propagated pixels will be treated by our proposed dual-way dynamic programming method for determining their disparities. In our proposed dual-way dynamic programming algorithm, the edge information will be taken into account as the energy minimization factor which will affect the results of the estimated disparity. In addition, several post processing techniques including occlusion handling, directional region voting, and edge-based temporal consistency are also adopted in this thesis to further improve the estimated disparity results with considering edge information. Simulation results demonstrate that our proposed disparity estimation algorithm not only improves the accuracy of the estimated disparity but also achieves less computational complexity consumptions and memory buffer requirements. On average, our proposed algorithm can achieve 34.48dB PSNR and reduce average 53.08 % of computation cost compared to the conventional dynamic programming method. Finally, the proposed algorithm is implemented in hardware form at 1920x1080@90fps and the synthesized gate count of our design is only 2,325K by using 90nm CMOS technology.