An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor

doi:10.1109/16.725260

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, HL	en_US
dc.contributor.author	Wu, CY	en_US
dc.date.accessioned	2019-04-02T05:59:35Z	-
dc.date.available	2019-04-02T05:59:35Z	-
dc.date.issued	1998-10-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/16.725260	en_US
dc.identifier.uri	http://hdl.handle.net/11536/150381	-
dc.description.abstract	An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFT's) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for wide gate voltage range.	en_US
dc.language.iso	en_US	en_US
dc.subject	GB states	en_US
dc.subject	grain-barrier height	en_US
dc.subject	grain size	en_US
dc.subject	intrinsic poly-Si TFT	en_US
dc.title	An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/16.725260	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	45	en_US
dc.citation.spage	2245	en_US
dc.citation.epage	2247	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000076221300021	en_US
dc.citation.woscount	40	en_US
顯示於類別：	期刊論文