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dc.contributor.authorHsiao, Yu-Chihen_US
dc.contributor.authorMeng, Chinchunen_US
dc.contributor.authorSyu, Jin-Siangen_US
dc.contributor.authorLin, Chung-Yoen_US
dc.contributor.authorWong, Shyh-Chyien_US
dc.contributor.authorHuang, Guo-Weien_US
dc.date.accessioned2019-04-02T06:04:37Z-
dc.date.available2019-04-02T06:04:37Z-
dc.date.issued2012-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/150603-
dc.description.abstractThis paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.en_US
dc.language.isoen_USen_US
dc.subjectlow poweren_US
dc.subjectdirect-conversion receiveren_US
dc.subjectvertical-NPN bipolar junction transistoren_US
dc.title5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corneren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)en_US
dc.citation.spage301en_US
dc.citation.epage304en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000318630900076en_US
dc.citation.woscount1en_US
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