Title: Scheduler design issues for wireless high-speed data systems
Authors: Huang, CY
Su, HY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: wireless;CDMA;data;1xEV-DO;3G;fairness;scheduler;data model;system throughput
Issue Date: 1-Jan-2004
Abstract: To understand the tradeoff between the system throughput and the user fairness, in this paper, two different scheduler design concepts are discussed and evaluated based on the full-buffer data model and finite packet-call-size data model. In finite packet-call-size data model, we will show analytically and by simulation that the system throughput depends on the number of active users and the user's in-slot rates. In order to quantify the impacts, a simulation platform is developed based on IxEV-DO technology.
URI: http://hdl.handle.net/11536/150680
Journal: 8TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIII, PROCEEDINGS: INDUSTRIAL SYSTEMS
Begin Page: 293
End Page: 298
Appears in Collections:Conferences Paper