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dc.contributor.authorAltolaguirre, Federico A.en_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2019-04-02T06:04:52Z-
dc.date.available2019-04-02T06:04:52Z-
dc.date.issued2013-01-01en_US
dc.identifier.issn2474-2724en_US
dc.identifier.urihttp://hdl.handle.net/11536/150685-
dc.description.abstractThe gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25 degrees C, and a ESD robustness of 3kV HBM and 200V MM.en_US
dc.language.isoen_USen_US
dc.titleUltra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000393052900069en_US
dc.citation.woscount0en_US
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