完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Li, Katherine Shu-Min | en_US |
dc.contributor.author | Chang, Yao-Wen | en_US |
dc.contributor.author | Su, Chauchin | en_US |
dc.contributor.author | Lee, Chung-Len | en_US |
dc.contributor.author | Chen, Jwu E. | en_US |
dc.date.accessioned | 2019-04-02T06:04:41Z | - |
dc.date.available | 2019-04-02T06:04:41Z | - |
dc.date.issued | 2006-01-01 | en_US |
dc.identifier.issn | 2153-6961 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/150802 | - |
dc.description.abstract | We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution. | en_US |
dc.language.iso | en_US | en_US |
dc.title | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS | en_US |
dc.citation.spage | 366 | en_US |
dc.citation.epage | 371 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000237227500075 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |