| 標題: | End-to-End Hardware Accelerator for Deep Convolutional Neural Network |
| 作者: | Chang, Tian-Sheuan 交大名義發表 National Chiao Tung University |
| 公開日期: | 1-Jan-2018 |
| URI: | http://hdl.handle.net/11536/150805 |
| ISSN: | 2474-2724 |
| 期刊: | 2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) |
| Appears in Collections: | Conferences Paper |
- 適用於卷積類神經網路之高效率硬體加速器設計 / 林岳縉;張添烜;Lin, Yue-Jin;Chang, Tian-Sheuan
- Data and Hardware Efficient Design for Convolutional Neural Network / Lin, Yue-Jin;Chang, Tian Sheuan
- A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things / Du, Li;Du, Yuan;Li, Yilei;Su, Junjie;Kuan, Yen-Cheng
- Design of Intelligent EEG System for Human Emotion Recognition with Convolutional Neural Network / Wang, Kai-Yen;Ho, Yun-Lung;Huang, Yu-De;Fang, Wai-Chi
- VSCNN: Convolution Neural Network Accelerator With Vector Sparsity / Chang, Kuo-Wei;Chang, Tian-Sheuan
- VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network / Chang, Kuo-Wei;Chang, Tian-Sheuan
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