標題: An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
作者: Chen, Pin-Wen
Huang, Chi-Wei
Wu, Chung-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: analog front-end;low noise;chopping;DC servo loop;SAR ADC;electroencephalogram (EEG)
公開日期: 1-Jan-2018
摘要: In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
URI: http://hdl.handle.net/11536/150860
ISSN: 0271-4302
期刊: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Appears in Collections:Conferences Paper