標題: | A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems |
作者: | Ng, Chee-Kit Lin, Yu-Chun Liu, Wei-Chang Wu, Chin-Feng Lou, Shyh-Lye 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-Jan-2018 |
摘要: | A 40Gb/s all-digital adaptive noise-suppression feed-forward filter/equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) systems is presented. Batch mode coefficients update (BMCU) unit together with coefficients-Iookahead scheme are proposed to achieve high parallelism architecture for ADFE. With these schemes, new extended incremental coefficients-Iookahead filter architecture is proposed to provide high throughput rate and to reduce hardware complexity of parallel ADFE. Besides, feed-forward noise-suppression architecture is proposed for AFFE to provide better signal-to-noise ratio (SNR). The equalizer operates at 1 GHz system clock with 40 parallelisms is implemented in 40nm CMOS technology with a core area 0.23mm(2). The measurement results verify the equalizer performance and the maximum throughput of 40Gb/s is achieved under 0.9V supply with 4.35pJ/bit energy efficiency. |
URI: | http://hdl.handle.net/11536/150868 |
ISSN: | 0271-4302 |
期刊: | 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Appears in Collections: | Conferences Paper |