Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization

Abstract

In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 mu s and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.