完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, Hao-Minen_US
dc.contributor.authorWen, Kuei-Annen_US
dc.date.accessioned2019-04-02T06:04:44Z-
dc.date.available2019-04-02T06:04:44Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn2163-9612en_US
dc.identifier.urihttp://hdl.handle.net/11536/150932-
dc.description.abstractThis paper presents a reconfigurable successive approximation register (SAR) Analog-to-Digital Converter (ADC) of which the resolution can be scaled from 9 to 12 bits for various inertial MEMS sensor applications. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In addition, level shifter connects the interface between digital and analog domain. 3 bit segmented capacitor array are used to decrease the static error and glitches from MSB switching. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 mu W and achieve 52.3, 57.7, 63.2 and 68.6 SNDR respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4fJ/conversion-step.en_US
dc.language.isoen_USen_US
dc.subjectSAR ADCen_US
dc.subjectMEMS sensoren_US
dc.subjectscaled resolutionen_US
dc.subjectdual voltageen_US
dc.subjectsegmented capacitor arrayen_US
dc.titleA Low Power Reconfigurable SAR ADC for CMOS MEMS Sensoren_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017)en_US
dc.citation.spage7en_US
dc.citation.epage8en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000454793100004en_US
dc.citation.woscount0en_US
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