完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Meng-Chen | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.contributor.author | Jou, Jing-Yang | en_US |
dc.date.accessioned | 2014-12-08T15:21:18Z | - |
dc.date.available | 2014-12-08T15:21:18Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.isbn | 978-1-61284-914-0 | en_US |
dc.identifier.issn | 1948-3295 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/15109 | - |
dc.description.abstract | Non-Manhattan structures, such as the X and Y architectures, propose different flavors in reducing the use of physical resources, such as total wirelength and number of vias. However, in order to take full advantage of these structures, we need to develop new tools for these architectures, especially for early stages in physical design. In this paper, we propose the packing algorithm with isosceles right triangular and trapezoidal blocks using the B*-tree representation. Our approach can be further applied to packing with any block which can be divided into rectangles and isosceles right triangles. Experimental results based on the modified MCNC benchmarks show that the average area usage is above 95% and the run time of our proposed algorithm is comparable when performing rectangular and non-rectangular block packing with original B*-tree. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) | en_US |
dc.citation.spage | 263 | en_US |
dc.citation.epage | 268 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000299054300041 | - |
顯示於類別: | 會議論文 |