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dc.contributor.authorWu, Meng-Chenen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorJou, Jing-Yangen_US
dc.date.accessioned2014-12-08T15:21:18Z-
dc.date.available2014-12-08T15:21:18Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-61284-914-0en_US
dc.identifier.issn1948-3295en_US
dc.identifier.urihttp://hdl.handle.net/11536/15109-
dc.description.abstractNon-Manhattan structures, such as the X and Y architectures, propose different flavors in reducing the use of physical resources, such as total wirelength and number of vias. However, in order to take full advantage of these structures, we need to develop new tools for these architectures, especially for early stages in physical design. In this paper, we propose the packing algorithm with isosceles right triangular and trapezoidal blocks using the B*-tree representation. Our approach can be further applied to packing with any block which can be divided into rectangles and isosceles right triangles. Experimental results based on the modified MCNC benchmarks show that the average area usage is above 95% and the run time of our proposed algorithm is comparable when performing rectangular and non-rectangular block packing with original B*-tree.en_US
dc.language.isoen_USen_US
dc.titleMixed Non-Rectangular Block Packing for Non-Manhattan Layout Architecturesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)en_US
dc.citation.spage263en_US
dc.citation.epage268en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000299054300041-
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