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dc.contributor.authorWong, Cheng-Chien_US
dc.contributor.authorLee, Yung-Yuen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2019-04-02T06:04:47Z-
dc.date.available2019-04-02T06:04:47Z-
dc.date.issued2009-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/151177-
dc.description.abstractThis paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.en_US
dc.language.isoen_USen_US
dc.subject3GPP LTEen_US
dc.subjectturbo decoderen_US
dc.subjectand QPP interleaveren_US
dc.titleA 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE Systemen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage288en_US
dc.citation.epage289en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000272335000115en_US
dc.citation.woscount10en_US
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