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dc.contributor.authorWeng, Yi-Pengen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorChen, Tung-Chiehen_US
dc.contributor.authorPan, Po-Chengen_US
dc.contributor.authorChen, Chien-Hungen_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2014-12-08T15:21:19Z-
dc.date.available2014-12-08T15:21:19Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4577-1398-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/15128-
dc.description.abstractThis paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.en_US
dc.language.isoen_USen_US
dc.titleFast Analog Layout Prototyping for Nanometer Design Migrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.citation.spage517en_US
dc.citation.epage522en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000299009100082-
Appears in Collections:Conferences Paper