完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Steve S. CHUNG | en_US |
dc.contributor.author | E-Ray HSIEH | en_US |
dc.date.accessioned | 2019-04-11T06:08:29Z | - |
dc.date.available | 2019-04-11T06:08:29Z | - |
dc.date.issued | 2018-10-11 | en_US |
dc.identifier.govdoc | H01L045/00 | en_US |
dc.identifier.govdoc | H01L027/24 | en_US |
dc.identifier.govdoc | G11C013/00 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/151442 | - |
dc.description.abstract | A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits. | en_US |
dc.language.iso | en_US | en_US |
dc.title | NONVOLATILE MEMORY AND ITS OPERATION METHOD THEREOF | en_US |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | en_US |
dc.citation.patentnumber | 20180294406 | en_US |
顯示於類別: | 專利資料 |