A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit

Abstract

A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/root Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.