Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, Yao-Lin | en_US |
dc.contributor.author | Lee, Jen-Wei | en_US |
dc.contributor.author | Liu, Po-Chun | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:21:21Z | - |
dc.date.available | 2014-12-08T15:21:21Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.isbn | 978-1-4244-9474-3 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/15167 | - |
dc.description.abstract | To enhance the data security in network communications, this paper presents a dual-field elliptic curve cryptographic processor (DECP) supporting all finite field operations and elliptic curve (EC) functions. Based on the fast radix-4 unified division algorithm, the execution time can be significantly reduced by a factor of three. By exploiting the hardware sharing and the ladder selection techniques, the proposed 160-bit and 256-bit DECP can have competitive execution cycle with only 0.29mm(2) and 0.45mm(2) silicon area in 90nm CMOS technology. In addition, the operating frequency in dual field can be increased by applying the data-path separation method and the degree checker. Our proposed DECP is over 2 similar to 6 times better in area-time product than relative works. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A Dual-Field Elliptic Curve Cryptographic Processor with a Radix-4 Unified Division Unit | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 713 | en_US |
dc.citation.epage | 716 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000297265300174 | - |
Appears in Collections: | Conferences Paper |