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dc.contributor.authorChen, Yao-Linen_US
dc.contributor.authorLee, Jen-Weien_US
dc.contributor.authorLiu, Po-Chunen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:21:21Z-
dc.date.available2014-12-08T15:21:21Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-9474-3en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/15167-
dc.description.abstractTo enhance the data security in network communications, this paper presents a dual-field elliptic curve cryptographic processor (DECP) supporting all finite field operations and elliptic curve (EC) functions. Based on the fast radix-4 unified division algorithm, the execution time can be significantly reduced by a factor of three. By exploiting the hardware sharing and the ladder selection techniques, the proposed 160-bit and 256-bit DECP can have competitive execution cycle with only 0.29mm(2) and 0.45mm(2) silicon area in 90nm CMOS technology. In addition, the operating frequency in dual field can be increased by applying the data-path separation method and the degree checker. Our proposed DECP is over 2 similar to 6 times better in area-time product than relative works.en_US
dc.language.isoen_USen_US
dc.titleA Dual-Field Elliptic Curve Cryptographic Processor with a Radix-4 Unified Division Uniten_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage713en_US
dc.citation.epage716en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000297265300174-
Appears in Collections:Conferences Paper