標題: High Resolution Comparator Design For RF Imager
作者: Pandey, Rajeev Kumar
Pandey, Sanjeev Kumar
電機資訊國際碩士學位學程
EECS International Graduate Program-Master
關鍵字: RF imager;Cascode Amplifier;SR Latch;Regenerative Latch;Comparator
公開日期: 1-Jan-2018
摘要: This paper proposes a design of high resolution regenerative latch based comparator for Multi Ramp Multi slope ADC of RF 3D imager. The minimum sense voltage for the design comparator is 500nV. A wide swing-self biased fully differential folded cascode amplifier used as analog front end for regenerative latch. Due to fully differential architecture of the comparator noise immunity is high. Simulation is done by using TSMC 0.18um with 1.8V supply. The total Power consumption of design comparator is 0.842mW and total delay is 11 mu s.
URI: http://hdl.handle.net/11536/151708
ISBN: 978-1-5386-7336-2
期刊: 2018 IEEE RECENT ADVANCES IN INTELLIGENT COMPUTATIONAL SYSTEMS (RAICS)
起始頁: 65
結束頁: 69
Appears in Collections:Conferences Paper