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dc.contributor.authorWeng, Jian-Jiaen_US
dc.contributor.authorWu, Mu-Chenen_US
dc.contributor.authorWang, Chung-Hsuanen_US
dc.contributor.authorSu, Yi-Shengen_US
dc.contributor.authorWu, Tsung-Chengen_US
dc.date.accessioned2014-12-08T15:21:21Z-
dc.date.available2014-12-08T15:21:21Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4577-0595-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/15175-
dc.description.abstractIn this paper, decoding of LDPC convolutional codes with rational parity-check matrices (LDPC-CC-RPCM) is investigated. We show that Tanner graph of every LDPC-CC-RPCM can always be transformed into an equivalent one with enlarged girth and finite memory order suitable for practical pipeline decoder. Based on the transformed graph, a dynamic scheduling-aided decoding scheme with the enhancement of signal perturbation and error cancellation is presented to improve the convergence speed and bit-error-rate performance in both of the waterfall and error-floor regions. Simulation results also reveal that LDPC-CC-RPCM may outperform ordinary LDPC-CC with polynomial parity-check matrices in some cases under the same code rate and decoding complexity.en_US
dc.language.isoen_USen_US
dc.titleDynamic Scheduling-Aided Decoding Strategies for LDPC Convolutional Codes with Rational Parity-Check Matricesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY PROCEEDINGS (ISIT)en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000297465102020-
Appears in Collections:Conferences Paper