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dc.contributor.authorMa, H. C.en_US
dc.contributor.authorChiu, J. P.en_US
dc.contributor.authorTang, C. J.en_US
dc.contributor.authorWang, Tahuien_US
dc.contributor.authorChang, C. S.en_US
dc.date.accessioned2014-12-08T15:21:22Z-
dc.date.available2014-12-08T15:21:22Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-2888-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/15192-
dc.identifier.urihttp://dx.doi.org/10.1109/IRPS.2009.5173223en_US
dc.description.abstractBipolar charge detrapping induced current instability in HfSiON gate dielectric pMOSFETs after negative bias and temperature stress is studied by using a fast transient measurement technique. Both single electron and single hole emissions are observed, leading to post-stress current degradation and recovery, respectively. The NBT stress voltage and temperature effect on post-stress current evolution is explored. Clear evidence of electron and hole trapping in NBT stress is demonstrated. A bipolar charge trapping/detrapping model and charge detrapping paths based on measured charge emission times are proposed.en_US
dc.language.isoen_USen_US
dc.titleInvestigation of Post-NBT Stress Current Instability Modes in HfSiON Gate Dielectric pMOSFETs by Measurement of Individual Trapped Charge Emissionsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/IRPS.2009.5173223en_US
dc.identifier.journal2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2en_US
dc.citation.spage51en_US
dc.citation.epage54en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000272068100008-
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