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dc.contributor.authorChang, Wei Lingen_US
dc.contributor.authorMeng, Chinchunen_US
dc.contributor.authorNi, Jung-Hungen_US
dc.contributor.authorCh, Kai-Chunen_US
dc.contributor.authorChang, Chih-Kaien_US
dc.contributor.authorLee, Po-Yien_US
dc.contributor.authorHuang, Yen-Linen_US
dc.date.accessioned2019-08-02T02:15:30Z-
dc.date.available2019-08-02T02:15:30Z-
dc.date.issued2019-07-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2019.2892065en_US
dc.identifier.urihttp://hdl.handle.net/11536/152203-
dc.description.abstractAnalytical noise formulations and design optimization of single- and dual-band inductively source-degenerated MOS low-noise amplifiers (LNAs) with the substrate and metal loss effects of on-chip inductors are established in this paper. It reveals that the noise figures of both single-/dual-band LNAs degrade substantially under the consideration of the loss effects. However, by increasing the device size, the noise optimization methodology of simultaneous noise and input match for a single-band LNA still holds true with concern for the loss effects. For a dual-band LNA, analytical noise optimization for a balanced noise design is established for inductors with metal and substrate loss and indicates a larger device size. The substrate and metal loss effects of inductors can be mitigated using integrated passive device (IPD) process for the input match network. The demonstrated single-band 0.18-mu m MOS LNAs with and without IPD process show noise figures of 1.53 and 2.52 dB at 2.4 GHz, respectively. Subsequently, the implemented dual-band 0.18-mu m MOS LNAs with and without IPD process show noise figures of 1.6/2.6 and 3.25/4.1 dB at 2.4/5 GHz, respectively.en_US
dc.language.isoen_USen_US
dc.subjectConcurrent dual-banden_US
dc.subjectinductoren_US
dc.subjectintegrated passive devices (IPD)en_US
dc.subjectloss effecten_US
dc.subjectlow noise amplifier (LNA)en_US
dc.subjectMOSen_US
dc.titleAnalytical Noise Optimization of Single-/Dual-Band MOS LNAs With Substrate and Metal Loss Effects of Inductorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2019.2892065en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume66en_US
dc.citation.issue7en_US
dc.citation.spage2454en_US
dc.citation.epage2467en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000472616100005en_US
dc.citation.woscount0en_US
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