用積體被動製程技術的CMOS低雜訊放大器與CMOS單刀雙擲開關設計

Abstract

本篇論文主要分為兩個主題，第一部分討論到低雜訊放大器設計，從第二章對MOSFET元件量測分析，對於電晶體本身的雜訊表現，與電晶體的最佳雜訊阻抗點，由量測分析可知，電晶體本身的雜訊貢獻，對電路表現並不如預期大，於是引發我們的好奇心，低雜訊放大器電路的雜訊貢獻來源為何，透過第三章的開頭，我們對於各種情況做出模擬探討，發現輸入端的匹配網路電感，由於非理想效應會對電路雜訊造成極大貢獻，於是，我們使用積體被動電路製程，替換製程電感，希望達到更好的雜訊表現，並在本章節，實際下線單頻帶、雙頻帶、寬頻帶低雜訊放大器電路，與CMOS 0.18 m製程比較。 論文第二部分主要探討單刀雙擲開關，單刀雙擲開關需要考慮到插入損耗、隔離度與功率承載能力。由於在TX端的前一級電路為功率放大器，會有著大功率傳輸，需要有著良好的功率承載能力，因此在本次設計使用Body Floating技術與汲源極端偏壓，提高其功率承載能力，並且有別於以往的對稱型形式，此次採用非對稱型單刀雙擲開關，有效提高TX端能力，並使用CMOS製程實際下線電路。

This thesis is mainly classified into two major parts: First, starting from Chapter 2, we discuss the measured results of MOSFET, especially the performance of noise figure and optimal noise impedance. From measured results, the MOSFET devices possess low noise but fail to perform low noise in the circuits. Thus, it is important to find the main reason of noise figure degradation in the circuits. In Chapter 3, we consider all situations through simulations. Then, we find that the main cause is the input matching inductance. Due to the mismatch and non-ideal effect, they will contribute the most noise in the circuit. As a result, we substitute inductances using integrated passive process for the input match inductors. This design can improve the noise figure of a low noise amplifier (LNA). Using single-band, dual-band and wide-band LNAs, the MOS LNAs with/without IPD are compared by CMOS 0.18 m process. Second, Single-pole Double Throw (SPDT) switches are discussed. A SPDT needs to take into considerations insertion loss (IL), isolation and power handling. A switch in front of a power amplifier must handle large power. Therefore, body floating method and increasing the bias voltage are employed. The asymmetric SPDT switches are designed using CMOS process.