實作並並回授與GIPD雙頻/寬頻FET低雜訊放大器

Abstract

本篇論文主要分為兩個主題，第一部分為並並回授低雜訊放大器的分析，第二部分為利用低損耗電感設計LC梯次輸入匹配低雜訊放大器。 第一部分主要討論電阻或電容並並回授的輸入匹配網路，接著利用雜訊轉換矩陣與雜訊參數來推導電容並並回授共源極電晶體的最低雜訊因子，並且透過模擬來驗證結果，最後，我們實作三顆並並回授寬頻低雜訊放大器，並且與其他不同輸入匹配架構的寬頻低雜訊放大器作比較。 第二部分介紹積體被動元件GIPD製程以及打線電感的原理與特點，接著透過模擬電感來觀察品質因子的改善，此外，針對不同操作頻段的LC梯次輸入匹配網路做模擬並討論雜訊指數的變化，最後，我們實作了兩顆使用GIPD整合0.18µm CMOS製程的低雜訊放大器以及一顆使用打線電感的低雜訊放大器，並與未使用低損耗電感的晶片作比較。

This thesis consists of two parts, the first part is the analysis of shunt-shunt feedback LNAs, and the second part is the design of LC-ladder input match LNAs utilizing low-loss inductors. In the first part, resistor and capacitor shunt-shunt feedback input match networks are discussed. Then, noise parameters of a common source FET device with a capacitor shunt-shunt feedback is derived utilizing noise transformation matrix. Furthermore, the results are verified by simulations. Finally, three shunt-shunt feedback LNAs are designed to compare with other LNAs with different input match networks. In the second part, the principle and characteristics of GIPD technology and bondwire inductors are introduced. The improvement of quality factor of inductors is observed from simulations. In addition, LC-ladder input match networks with different values of components are simulated to discuss the effect to the noise figure. Finally, two LNAs using GIPD 0.18µm CMOS process and one LNA using bondwire inductors are designed to compare with LNAs using standard CMOS process.