FET低雜訊放大器設計最佳化與5/60-GHz 0.18-um CMOS雙模態雙轉換接收機

Abstract

本論文使用雜訊矩陣來解析雜訊公式並提出單頻帶、雙頻帶及寬頻帶源級退化共源極FET低雜訊放大器的最佳化設計理論。雙頻帶及寬頻帶LC梯式低雜訊放大器的雜訊公式可使用雜訊矩陣直接於單頻帶低雜訊放大器做延伸，經由推導的雜訊公式可證明單頻帶低雜訊放大器可同時達到阻抗及雜訊匹配於同一頻帶，而雙頻帶低雜訊放大器則無法同時雜訊匹配於其兩操作頻帶，因而，平衡兩頻帶的雜訊設計則使用雜訊矩陣於本論文發展出。根據雜訊轉換矩陣的解析方法，寬頻LC梯式源級退化低雜訊放大器的雜訊公式及其對應的雜訊匹配網路可直接發展出，基於建立的雜訊匹配網路及LC梯式柴比雪夫濾波器的設計概念，寬頻低雜訊放大器的最佳化設計方法亦提出於論文中。本論文提出的低雜訊放大器最佳化設計演算法可適用於所有的FET元件中，諸如MOSFET、 MESFET 及 HEMT 元件中。最後，本論文實作了5 GHz單頻帶、 2.4/5 GHz 共存式雙頻帶及3~10 GHz寬頻帶單壓操作低雜訊放大器於0.15 um pHEMT 製程來驗證設計理論。 另一方面，本論文提出一個具有兩載子頻率差異甚遠且通帶頻寬差異極大的5 GHz及60 GHz雙模態雙轉頻接收機於標準0.18 μm CMOS製程當中。雙轉頻的架構使用蕭特基二極體於第一次轉頻級來接收60 GHz模態而整合5 GHz模態於第二次轉頻級。60 GHz模態的十億赫茲級通道選擇可於最後第二中頻級來達成，而窄頻的主動濾波器被植入5 GHz低雜訊放大器與第二轉頻級之間伴隨著5 GHz模態的千萬赫茲級的通道選擇於5 GHz的射頻路徑上，射頻通道選取於5 GHz的方式可克服中頻通道選取所需面對的增益語頻寬調諧的問題。 此外，本論文也使用0.18 um SiGe BiCMOS製程實現一個 具兩傳輸零點可調式2.4 GHz主動帶通濾波器。此提出的架構使用了集總式環形結構並加入微擾電容來產生兩傳輸零點於截止頻帶中。為了改善通帶內的植入損耗，變壓器耦合式的品質因子增強型電路被應用來提升晶片電感的品質因子，再者，經由可變電容的設計可達到操作頻率可調的特性。

This thesis describes the design optimization of single-band, dual-band and broadband inductively source-degenerated common-source FET LNAs using analytical formula of noise parameters derived through noise transformation matrix. The dual-band and broadband LC-ladder LNA designs can be directly expanded from the single-band LNA design using noise transformation matrix. The derived noise formulas of LNAs reveal that a simultaneous noise and input match can be obtained at a single frequency for a single-band LNA. For a concurrent dual-band LNA, the simultaneous noise match cannot be achieved at two different operating frequencies and thus a balanced design in noise performance is developed using noise transformation matrix. According to noise transformation matrix analytical method, the noise formulas of a broadband LC-ladder inductively source-degenerated common-source LNA and the related noise match network can be straightforwardly developed. Based on the established noise match network and well-known LC-ladder Chebyshev filter design method, the design optimization of the broadband LNA is also presented in this thesis. The presented optimal design algorithm of single-/dual-/broad-band LNAs can be applied to all of the FET devices such as MOSFET, MESFET and HEMT device. Finally, this thesis demonstrates a 5 GHz single-band, a 2.4/5 GHz concurrent dual-band and a 3~10 GHz broadband single-voltage-supply LNAs using 0.15 um pHEMT technology to verify design methodology. This thesis also presents a dual-mode dual-conversion receiver with two far-apart carrier frequencies, 5 GHz and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, in the standard 0.18 μm CMOS technology. The dual conversion architecture receives the 60 GHz mode using Schottky diodes at the first conversion stage and merges the 5 GHz mode at the second stage conversion. The GHz channel bandwidth selection of 60 GHz mode is achieved at the final IF2 stage while a narrow band active filter is inserted between the 5 GHz low-noise amplifier (LNA) and the second stage mixer to accomplish tens-MHz channel selection of 5 GHz mode in the 5 GHz RF path. The overlay of tens-MHz channel selection in the 5 GHz RF path with GHz channel selection in the final IF2 stage eliminates the severe gain-bandwidth trade-offs encountered if the tens-MHz channel selection is also done at the final IF2 stage. In addition, a 2.4 GHz tunable active bandpass filter with two transmission zeros using the 0.18 um SiGe BiCMOS technology is also demonstrated in this thesis. The presented circuit topology employs a lumped ring structure and adds a perturbation capacitor to insert two transmission zeros for stopband rejection. To improve the passband insertion loss, a transformer-coupled Q-enhanced technique is employed to boost the Q-factor of the on-chip inductor. Moreover, three varactors are inserted in the filter design to achieve frequency tuning of the filter.